Effects of Scaling of Junctionless Transistor Parameters with Silicon Dioxide (Sio2) and Silicon Nitrate (Si3N4) Gate Oxides on the Electrical Characteristics of the Devices
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This research investigated the effects of scaling of parameters of junctionless transistors (JLT) with SiO2 gate oxide and Si3N4 gate oxide on the electrical characteristics of the two devices. It also compared the electrical performance of the two devices as a way of replacing the conventional SiO2 gate oxide with high-k dielectric such as Si3N4 gate oxide. Different JLT were designed and simulated using a technology computer aided device software, sentaurus and extracted the electrical characteristics such as Threshold voltage, subthreshold slope, drain induced barrier lowering, on-state current etc. It was observed that leakage current, DIBL, SS as well as on-state current were significantly improved using Si3N4 as gate oxide in JLT. As a result, on-state to off-state current ratio was greatly increased, hence the speed of the device. The performance was significantly increased to approximately 109 using Si3N4 material for gate length of 10nm and nanowire diameter of 10nm. All these were achieved because of the high dielectric constant, k of the Si3N4 which is higher than that of SiO2. Similarly, Si3N4 has also has high energy band gap which considerably help in reducing the leakage current and other short channel effects (SCEs).
2. J.-P. Colinge et al., "Junctionless nanowire transistor (JNT): Properties and design guidelines," Solid-State Electronics, vol. 65, pp. 33-37, 2011.
3. J.-P. Colinge, "Junctionless transistors," in 2012 IEEE International Meeting for Future of Electron Devices, Kansai, 2012, pp. 1-2: IEEE.
4. B. Ghosh and M. W. Akram, "Junctionless tunnel field effect transistor," IEEE electron device letters, vol. 34, no. 5, pp. 584-586, 2013.
5. A. Nowbahari, A. Roy, and L. Marchetti, "Junctionless transistors: State-of-the-art," Electronics, vol. 9, no. 7, p. 1174, 2020.
6. B.-H. Lee et al., "A vertically integrated junctionless nanowire transistor," Nano letters, vol. 16, no. 3, pp. 1840-1847, 2016.
7. B. H. Lee et al., "Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application," in International Electron Devices Meeting 1999. Technical Digest (Cat. No. 99CH36318), 1999, pp. 133-136: IEEE.
8. N. E. Alias et al., "Electrical characterization of n-type cylindrical gate all around nanowire junctionless transistor with SiO2 and high-k dielectrics," in 2020 IEEE International Conference on Semiconductor Electronics (ICSE), 2020, pp. 13-16: IEEE.
9. J. C. Pravin, P. Prajoon, F. P. Nesamania, G. Srikesh, P. Senthil Kumar, and D. Nirmal, "Nanoscale high-k dielectrics for junctionless nanowire transistor for drain current analysis," Journal of Electronic Materials, vol. 47, no. 5, pp. 2679-2686, 2018.
10. N. B. Bousari, M. K. Anvarifard, and S. Haji-Nasiri, "Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering," AEU-International Journal of Electronics and Communications, vol. 108, pp. 226-234, 2019.
11. G. Dhiman, R. Pourush, and P. Ghosh, "Performance analysis of high-κ material gate stack based nanoscale junction less double gate MOSFET," Materials Focus, vol. 7, no. 2, pp. 259-267, 2018.
